The schematic cross-sectional view of the FDMOS is proposed in Fig. In addition, compared with the conventional method of using an externally connected Schottky diode as an FWD, the integrated fin-shaped diode doesn’t occupy the extra chip area and introduce parasitic inductance. MOS) with a body diode as a FWD, the V ON and Q rr of the FDMOS are significantly reduced. Compared with the conventional MOSFET (Con. In this paper, a novel vertical GaN MOSFET with integrated fin-shaped diode (FDMOS) is proposed to improve the reverse conduction characteristic. It decreases the number of parasitic components and simplifies packaging, but the leakage current in the off-state is a drawback nevertheless. One solution is the monolithically integration of the SBD. However, the large parasitic inductance is introduced, resulting in the extra power loss and system instability. Using an external anti-paralleled Schottky barrier diode (SBD) as a freewheeling diode (FWD) for reverse conduction is easy to reduce V ON. Moreover, the P-i-N diode is bipolar device, and its rise time ( t r) and fall time ( t f) are very large, owing to the large reverse recovery charge ( Q rr) during on/off transition. The typical turn-on voltage ( V ON) of the body diode in Si MOSFET is only 0.7 V, while the typical V ON of the GaN PiN diode is close to 3 V. įor practical use of the vertical transistors in topologies of power converters (e.g., buck/boost converters), reverse conduction with low loss is also demanded to release the surplus energy induced by the inductive load. The vertical transistors can make full use of the potential of GaN material for high breakdown voltage. However, owing to the high-density interface states and high surface electric field (E-field) peak, the lateral HEMTs normally suffer from severe stability and reliability issues. Many researches focus on lateral high electron mobility transistors (HEMTs) because of its high-density and high-mobility two-dimensional electron gas (2DEG), which allows high-voltage devices with low on-resistance and high switching speed. GaN-based devices are excellent candidates for power devices due to high critical electric field, high electron mobility and high-temperature operation. In addition, the FDMOS is beneficial to reduce the parasitic inductance and the total chip area compared with the conventional method of using an externally connected Schottky diode as an FWD. The Q GD, the turn-on loss ( E on) and the turn-off loss ( E off) of the FDMOS are decreased by 56.8%, 33.8% and 53.8%, respectively, compared with those of the Con. The gate charge ( Q GD) of the FDMOS is significantly reduced because the fin structure reduces the gate area and transforms some part of C GD to C GS, and thus, a low switching loss is realized. MOS, without the minority carrier injection. Moreover, the Q rr of the FDMOS is reduced to 1.36 μC from 1.64 μC of the Con. MOS) with a body diode as a freewheeling diode (FWD), the FDMOS uses the integrated fin-shaped diode to reverse conduction, and thus, a low reverse turn-on voltage V ON of 0.66 V is achieved, with a decreasing of 77.9%. Its static and dynamic characteristics are studied and analyzed by Sentaurus TCAD simulation. A vertical GaN power MOSFET featuring an integrated fin-shaped non-junction diode (FDMOS) is proposed to improve reverse conduction and switching characteristics.
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